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| ? 1996 microchip technology inc. preliminary ds40152c-page 1 m code hopping encoder features security programmable 28/32-bit serial number programmable 64-bit encryption key each transmission is unique 67-bit transmission code length 32-bit hopping code 35-bit ?ed code (28/32-bit serial number, 4/0-bit function code, 1-bit status, 2-bit crc) encryption keys are read protected operating 2.0-6.6v operation four button inputs - 15 functions available selectable baud rate automatic code word completion battery low signal transmitted to receiver nonvolatile synchronization data pwm and manchester modulation other easy to use programming interface on-chip eeprom on-chip oscillator and timing components button inputs have internal pull-down resistors current limiting on led output minimum component count enhanced features over hcs300 48-bit seed vs. 32-bit seed 2-bit crc for error detection 28/32-bit serial number select two seed transmission methods pwm and manchester modulation ir modulation mode typical applications the HCS360 is ideal for remote keyless entry (rke) applications. these applications include: automotive rke systems automotive alarm systems automotive immobilizers gate and garage door openers identity tokens burglar alarm systems package types HCS360 block diagram description the HCS360 is a code hopping encoder designed for secure remote keyless entry (rke) systems. the HCS360 utilizes the k ee l oq code hopping technology, which incorporates high security, a small package outline and low cost, to make this device a perfect solution for unidirectional remote keyless entry systems and access control systems. the HCS360 combines a 32-bit hopping code generated by a nonlinear encryption algorithm, with a 28/32-bit serial number and 7/3 status bits to create a 67-bit transmission stream. the length of the transmission eliminates the threat of code scanning and the code hopping mechanism makes each transmission unique, thus rendering code capture and resend (code grabbing) schemes useless. 1 2 3 4 8 7 6 5 s0 s1 s2 s3 v dd led pwm v ss pdip, soic HCS360 v ss v dd oscillator reset circuit led driver controller power latching and switching button input port 32-bit shift register encoder eeprom pwm led s 3 s 2 s 1 s 0 HCS360 k ee l oq is a registered trademark of microchip technology inc. *code hopping encoder patents issued in europe, u. s. a., r. s. a. ?us: 5,517,187; europe: 0459781
HCS360 ds40152c -page 2 preliminary ? 1996 microchip technology inc. the encr yption k e y , ser ial n umber , and con gur ation data are stored in eepr om which is not accessib le via an y e xter nal connection. this mak es the HCS360 a v er y secure unit. the HCS360 pro vides an easy to use ser ial interf ace f or prog r amming the necessar y secur ity k e ys , system par ameters , and con gur ation data. the encr yption k e ys and code combinations are pro- g r ammab le b ut read-protected. the k e ys can only be v er i ed after an automatic er ase and prog r amming oper ation. this protects against attempts to gain access to k e ys and manipulate synchronization v alues . the HCS360 oper ates o v er a wide v oltage r ange of 2.0v to 6.6v and has f our b utton inputs in an 8-pin con gur ation. this allo ws the system designer the freedom to utiliz e up to 15 functions . the only components required f or de vice oper ation are the b ut- tons and rf circuitr y , allo wing a v er y lo w system cost. 1.0 system o ver vie w 1.1 k e y t erms man uf acturer s code ?a 64-bit w ord, unique to each man uf acturer , used to produce a unique encr yption k e y in each tr ansmitter (encoder). encr yption k e y ?a unique 64-bit k e y gener ated and prog r ammed into the encoder dur ing the man uf actur ing process . the encr yption k e y controls the encr yption algor ithm and is stored in eepr om on the encoder de vice . lear n ? t he hcs product f amily f acilitates se v er al lear n ing str ategies to be implemented on the decoder . the f ollo wing are e xamples of what can be done . nor mal lear ning the receiv er uses the same inf or mation that is tr ansmitted dur ing nor mal oper ation to der iv e the tr ansmitter s secret k e y , decr ypt the discr imination v alue and the synchronization counter . secure lear n* the tr ansmitter is activ ated through a special b ut- ton combination to tr ansmit a stored 48-bit v alue (r andom seed) that can be used f or k e y gener a- tion or be par t of the k e y . t r ansmission of the r an- dom seed can be disab led after lear ning is completed. the HCS360 is a code hopping encoder de vice that is designed speci cally f or k e yless entr y systems , pr imar ily f or v ehicles and home gar age door openers . it is meant to be a cost-eff ectiv e , y et secure solution to such systems . the encoder por tion of a k e yless entr y system is meant to be held b y the user and oper ated to gain access to a v ehicle or restr icted area. the HCS360 requires v er y f e w e xter nal components ( figure 2-1 ). most k e yless entr y systems tr ansmit the same code from a tr ansmitter e v er y time a b utton is pushed. the relativ e n umber of code combinations f or a lo w end sys- tem is also a relativ ely small n umber . these shor tcomings pro vide the means f or a sophisticated thief to create a de vice that ? r abs a tr ansmission and retr ansmits i t later or a de vice that scans all possib le combinations until the correct one is f ound. the HCS360 emplo ys the k ee l oq code hopping tech- nology and an encr yption algor ithm to achie v e a high le v el of secur ity . code hopping is a method b y which the code tr ansmitted from the tr ansmitter to the receiv er is diff erent e v er y time a b utton is pushed. this method, coupled with a tr ansmission length of 67 bits , vir tually eliminates the use of code ? r ab bing or code scanning? as indicated in the b loc k diag r am on page one , the HCS360 has a small eepr om arr a y which m ust be loaded with se v er al par ameters bef ore use . the most impor tant of these v alues are: a 28/32-bit ser ial n umber which is meant to be unique f or e v er y encoder an encr yption k e y that is gener ated at the time of production a 16-bit synchronization v alue the ser ial n umber f or each tr ansmitter is prog r ammed b y the man uf acturer at the time of production. the gener ation of the encr yption k e y is done using a k e y gener ation algor ithm ( figure 1-1 ). t ypically , inputs to the k e y gener ation algor ithm are the ser ial n umber of the tr ansmitter or seed v alue , and a 64-bit man uf ac- turer s code . the man uf acturer s code is chosen b y the system man uf acturer and m ust be carefully controlled. the man uf acturer s code is a piv otal par t of the o v er all system secur ity . the 16-bit synchronization v alue is the basis f or the tr ansmitted code changing f or each tr ansmission, and is updated each time a b utton is pressed. because of the comple xity of the code hopping encr yption algo- r ithm, a change in one bit of the synchronization v alue will result in a large change in the actual tr ansmitted code . there is a relationship ( figure 1-2 ) betw een the k e y v alues in eepr om and ho w the y are used in the encoder . once the encoder detects that a b utton has been pressed, the encoder reads the b utton and updates the synchronization counter . the synchroniza- tion v alue is then combined with the encr yption k e y in the encr yption algor ithm and the output is 32 bits of encr ypted inf or mation. this data will change with e v er y b utton press , hence , it is ref erred to as the hopping por tion of the code w ord. the 32-bit hopping code is combined with the b utton inf or mation and the ser ial n umber to f or m the code w ord tr ansmitted to the receiv er . the code w ord f or mat is e xplained in detail in section 4.2 . *secure lear ning patents pending. HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 3 an y type of controller ma y be used as a receiv er , b ut it is typically a microcontroller with compatib le r mw are that allo ws the receiv er to oper ate in conjunction with a tr ansmitter , based on the HCS360 . section 7.0 pro vides more detail on integ r ating the HCS360 into a total system. bef ore a tr ansmitter can be used with a par ticular receiv er , the tr ansmitter m ust be ?ear ned b y the receiv er . upon lear ning a tr ansmitter , inf or mation is stored b y the receiv er so that it ma y tr ac k the tr ansmitter , including the ser ial n umber of the tr ansmitter , the current synchronization v alue f or that tr ansmitter and the same encr yption k e y that is used on the tr ansmitter . if a receiv er receiv es a message of v alid f or mat, the ser ial n umber is chec k ed and, if it is from a lear ned tr ansmitter , the message is decr ypted and the decr ypted synchronization counter is chec k ed against what is stored. if the synchronization v alue is v er i ed, then the b utton status is chec k ed to see what oper ation is needed. figure 1-3 sho ws the relationship betw een some of the v alues stored b y the receiv er and the v al- ues receiv ed from the tr ansmitter . figure 1-1: creation and stora g e of encr yption k e y during pr oduction figure 1-2: basic operation of t ransmitter (encoder) figure 1-3: basic operation of receiver (decoder) t r ansmitter man uf acturer s ser ial number or code encr yption k e y k e y gener ation algor ithm ser ial number encr yption k e y sync counter . . . HCS360 eepr om arr a y seed k ee l oq algor ithm button press inf or mation encr yption eepr om arr a y 32 bits of encr ypted data ser ial number t r ansmitted inf or mation decr yption k e y sync counter ser ial number button press inf or mation eepr om arr a y dec r yption k e y 32 bits of encr ypted data ser ial number receiv ed inf or mation decr ypted synchronization counter chec k f or match chec k f or match k ee l oq algor ithm de cr yption sync counter ser ial number man uf acturer code HCS360 ds40152c -page 4 preliminary ? 1996 microchip technology inc. 2.0 de vice operation as sho wn in the typical application circuits ( figure 2-1 ), the HCS360 is a simple de vice to use . it requires only the addition of b uttons and rf circuitr y f or use as the tr ansmitter in y our secur ity application. a descr iption of each pin is descr ibed in t ab le 2-1 . figure 2-1: typical cir cuits t able 2-1 pin descriptions the high secur ity le v el of the HCS360 is based on the patented k ee l oq technology . a b loc k cipher type of encr yption algor ithm based on a b loc k length of 32 bits and a k e y length of 64 bits is used . the algor ithm obscures the inf or mation in such a w a y that e v en if the tr ansmission inf or mation (bef ore coding) diff ers b y only one bit from the inf or mation in the pre vious tr ansmis- sion, the ne xt coded tr ansmission will be totally diff er- ent. statistically , if only one bit in the 32-bit str ing of inf or mation changes , appro ximately 50 percent of the coded tr ansmission will change . the HCS360 will w ak e up upon detecting a s witch closure and then dela y appro ximately 6.5 ms f or s witch debounce ( figure 2-2 ). the synchroniz ation i nf or mation, x ed inf or mation, and s witch inf or mation will be encr ypted to f or m the hopping code . the encr ypted or hopping code por tion of the tr ansmission will change e v er y time a b utton is pressed, e v en if the same b utton is pushed again. k eeping a b utton pressed f or a long time will result in the same code w ord being tr ansmitted until the b utton is released or time-out o ccurs . a code that has been tr ansmitted will not occur again f or more than 6 4k tr ansmissions . this will pro vide more than 18 y ears of typical use bef ore a code is repeated based on 10 oper- ations per da y . ov er o w inf or mation prog r ammed into the encoder can be used b y the decoder to e xtend the n umber of unique tr ansmissions to more than 128 k . if , in the tr ansmit process , it is detected that a ne w b ut- ton(s) has been pressed, a reset will immediately be f orced and the code w ord will not be completed. please note that b uttons remo v ed will not ha v e an y eff ect on the code w ord unless no b uttons remain pressed in which case the current code w ord will be completed and the po w er do wn will occur . name pin number description s0 1 switch input 0 s1 2 switch input 1 s2 3 switch input 2 /can also be cloc k pin when in prog r amming mode s3 4 switch input 3/ c loc k pin when in prog r amming mode v ss 5 ground ref erence connection pwm 6 pulse width modulation (pwm) output pin/data pin f or prog r amming mode led 7 cathode connection f or directly dr iving led dur ing tr ansmission v dd 8 p ositiv e supply v oltage connection v dd b0 tx out s0 s1 s2 s3 led v dd pwm v ss 2 b utton remote control b1 v dd tx out s0 s1 s2 s3 led v dd pwm v ss 5 b utton remote control (note) b4 b3 b2 b1 b0 note: up to 15 functions can be implemented b y pressing more than one b utton sim ulta- neously or b y using a suitab le diode arr a y . HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 5 figure 2-2: encoder operation 3.0 eepr om memor y or ganization the HCS360 contains 192 bits (12 x 16-bit w ords) of eepr om memor y ( t ab le 3-1 ). this eepr om arr a y is used to store the encr yption k e y inf or mation, synchronization v alue , etc. fur ther descr iptions of the memor y arr a y is giv en in the f ollo wing sections . t able 3-1 eepr om memor y map 3.1 k e y_0 - k e y_3 (64-bit encr yption k e y) the 64-bit encr yption k e y is used b y the tr ansmitter to create the encr ypted message tr ansmitted to the receiv er . this k e y is created and prog r ammed at the time of production using a k e y gener ation algor ithm. inputs to the k e y gener ation algor ithm are the ser ial n umber f or the par ticular tr ansmitter being used and a secret m an uf acturer s code . while the k e y gener ation algor ithm supplied from microchip is the typical method used, a user ma y elect to create their o wn method of k e y gener ation. this ma y be done pro viding that the decoder is prog r ammed with the same means of creat- ing the k e y f or decr yption pur poses . if a seed is used, the seed will also f or m par t of the input to the k e y gen- er ation algor ithm. p o w er up reset and debounce dela y ( 6.5 m s) sample inputs update sync inf o encr ypt with load t r ansmit register button s added ? all buttons released ? (a b utton has been pressed) t r ansmit stop no y es no y es encr yption k e y complete code w ord t r ansmission w ord address mnemonic description 0 key_0 64-bit e ncr yptio n k e y ( w ord 0) 1 key_1 64-bit encr yptio n k e y ( w ord 1) 2 key_2 64-bit encr yptio n k e y ( w ord 2) 3 key_3 64-bit encr yptio n k e y ( w ord 3) 4 sync_a 16-bit synchroniza- tion v alue 5 sync_b/s eed _ 2 16-bit synchroniza- tion or seed v alue (w ord 2) 6 reser ved set to 0000h 7 se ed_ 0 seed v alue ( w ord 0) 8 se ed_ 1 seed v alue ( w ord 1) 7 se r_ 0 de vice ser ial number ( w ord 0) 10 se r_ 1 de vice ser ial number ( w ord 1) 11 config con g ur ation w ord HCS360 ds40152c -page 6 preliminary ? 1996 microchip technology inc. 3.2 sync_a, sync_b (sync hr onization counter) this is the 16-bit synchronization v alue that is used to create the hopping code f or tr ansmission. this v alue will be changed after e v er y tr ansmission. a second syn- chronization v alue c an be used to sta y synchroniz ed with a second receiv er . 3.3 seed_0, seed_1, and seed_2 (seed w or d) this is the t hree w ord ( 48 b its) seed code that will be tr ansmitted when seed tr ansmission is selected. this allo ws the system designer to implement the secure lear n f eature or use this x ed code w ord as par t of a diff erent k e y gener ation/tr ac king process or purely as a x ed code tr ansmission . 3.4 ser_0, ser_1 (encoder serial number) ser_0 and ser_1 are the lo w er and upper w ords of the de vice ser ial n umber , respectiv ely . there are 32 bits allocated f or the ser ial n umber and a selectab le con g- ur ation bit deter mines whether 32 or 28 bits will be tr ansmitted. the ser ial n umber is meant to be unique f or e v er y tr ansmitter . 3.5 config (con guration w or d) the con gur ation w ord is a 16-bit w ord stored in eepr om arr a y that is used b y the de vice to store inf or mation used dur ing the encr yption process , as w ell as the status of option con gur ations . fur ther e xplanations of each of the bits are descr ibed in the f ollo wing sections . 3.5.1 lngrd: long guard time lngrd = 1 selects the encoder to e xtend the guard time betw een code w ords . this can be used to reduce the a v er age po w er tr ansmitted o v er a 100ms windo w and thereb y tr ansmit a higher peak po w er . 3.5.2 f ast 1, f ast 0 baud rate selection f ast 1 and f ast 0 selects the baud r ate according to t ab le 3-3 . t able 3-3 baud rate selection t able 3-2 configuration w or d bit number symbol bit description 0 lngrd long guard time 1 f ast 0 baud rate selection 2 f ast 1 baud rate selection 3 nu not used 4 seed seed t r ansmission enab le 5 delm dela y mode enab le 6 timo time out enab le 7 ind independent mode enab le 8 usra0 user bit 9 usra1 user bit 10 usrb0 user bit 11 usrb1 user bit 12 xser extended ser ial n umber enab le 13 tmpsd t empor ar y seed tr ansmis- sion enab le 14 manch manchester/pwm modula- tion selection 15 o vr ov er o w bit t e f ast 1 f ast 0 400 0 0 200 0 1 200 1 0 100 1 1 HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 7 3.5.3 seed: enab le seed t r ansmission if seed = 0, seed tr ansmission is disab led. the inde- pendent counter mode can only be used with seed tr ansmission disab led since seed_2 is shared with the second synchronization counter . w ith seed = 1, seed tr ansmission is enab led. the appropr iate b utton code(s) m ust be activ ated to tr ans- mit the seed inf or mation. in this mode , the seed inf or- mation (seed_0, seed_1, and seed_2) and the upper 12- or 16-bits of the ser ial n umber (ser_1) a re tr ansmitted instead of the hop code . seed tr ansmission is a v ailab le f or function codes ( t ab le 3-7 ) s[3:0] = 1001 and s[3:0] = 0011(dela y ed). this tak es place regardless of the setting of the ind bit. the tw o seed tr ansmissions are sho wn in figure 3-1 . figure 3-1: seed t ransmission all e xamples sho wn with xser = 1, seed = 1 when s[3:0] = 1001 , dela y is not acceptab le . crc+ v low ser_1 seed_2 seed_1 seed_0 data tr ansmission direction f or s[3:0] = 0x 3 bef ore dela y: 16-bit data w ord 16-bit counter encr ypt crc+ v low ser_1 ser_ 0 encr ypted data f or s[3:0] = 0011 after dela y (note 1, note 2): crc+ v low ser_1 seed_2 seed_1 seed_0 data tr ansmission direction data tr ansmission direction note 1: f or seed t r ansmission, seed_2 is tr ansmitted instead of ser_0. 2: f or seed t r ansmission, the setting of delm has no eff ect. HCS360 ds40152c -page 8 preliminary ? 1996 microchip technology inc. 3.5.4 delm: dela y mode if delm = 1, dela y tr ansmission is enab led. a dela y ed tr ansmission is indicated b y in v er ting the lo w er nib b le of the discr imination v alue . the dela y mode is pr imar ily f or compatibility with pre vious k ee l oq de vices . i f delm = 0, dela y tr ansmission is disab led ( t ab le 3-4 ). 3.5.5 t imo: time-out if timo = 1, the time-out is enab led. time-out can be used to ter minate accidental contin uous tr ansmissions . when time-out occurs , the pwm output is set lo w and the led is tur ned off . current consumption will be higher than in standb y mode since current will o w through the activ ated input resistors . this state can be e xited only after all inputs are tak en lo w . timo = 0, will enab le contin uous tr ansmission ( t ab le 3-5 ). t able 3-4 t ypical dela y times f ast1 f ast0 number of code w or ds bef ore dela y mode time bef ore dela y mode (manch = 0) time ref dela y mode (manch = 1) 0 0 28 ? 2.9s ? 5.1s 0 1 56 ? 3.1s ? 6.4s 1 0 28 ? 1.5s ? 3.2s 1 1 56 ? 1.7s ? 4.5s t able 3-5 t ypical time-out times f ast 1 f ast 0 maxim um number of code w or ds t ransmitted time bef ore time-out (manch = 0) time bef ore time-out (manch = 1) 0 0 256 ? 26.5s ? 46.9 0 1 512 ? 28.2s ? 58.4 1 0 256 ? 14.1s ? 29.2 1 1 512 ? 15.7s ? 40.7 HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 9 3.5.6 ind: independent mode the independent mode can be used where one encoder is used to control t w o receiv ers . t w o counters ( sync_a a nd sync_b) are used in independent mode . as indicated in t ab le 3-7 , function codes 1 to 7 use sync_a and 8 to 1 5 sync_b . the independent mode also select s ir mode . in ir mode function codes 12 to 15 will use sync_b . the pwm output signal is modulated with a 40 khz carr ier . it m ust be pointed out the 40 khz is der iv ed from the inter nal cloc k and will theref ore v ar y with the same percentage as the baud r ate . if ind = 0, sync_a i s used f or all function codes . if ind = 1, independent mode is enab led and counters f or functions are used according to t ab le 3-7 . f or ind = 1 and s[3:0] o 0xc , 0xd , 0xe, 0xf , basic pulse width modulation becomes: 3.5.7 usra,b: user bits user bits f or m par t of the discr imination v alue . the use r bits together with the ind bit can be used to identify the counter that is used in independent mode . 3.5.8 xser: extended ser ial number if xse r = 1, the full 32-bit ser ial n umber [ser_1, s er _0] is tr ansmitted. if xser = 0, the f our most sig- ni cant bits of the ser ial n umber are substituted b y s[ 3:0] and is compatib le with the hcs200/300/301. 3.5.9 tmpsd: t empor ar y seed t r ansmission the tempor ar y seed tr ansmission can be used to dis- ab le lear ning after the tr ansmitter has been used f or a prog r ammab le n umber of oper ations . this f eature can be used to implement v er y secure systems . after lear n- ing is disab led, the seed inf or mation cannot be accessed e v en if ph ysical access to the tr ansmitter is possib le . if tmpsd = 1 the seed tr ansmission will be disab led after a n umber of code hopping tr ansmissions . the n umber of tr ansmissions bef ore seed tr ansmission is disab led, can be prog r ammed b y setting the synchro- nization counter (sync_a, sync_b) to a v alue as sho wn in t ab le . t able 3-6 sync hr onous counter initialization v alues sync hr onous counter v alues number of t ransmissions 0000h 128 0060h 64 005 0h 32 0048h 16 t able 3-7 function codes s3 s2 s1 s0 ind = 0 ind = 1 comments counter 1 0 0 0 1 a a 2 0 0 1 0 a a 3 0 0 1 1 a a if seed = 1, tr ansmit seed after dela y . 4 0 1 0 0 a a 5 0 1 0 1 a a 6 0 1 1 0 a a 7 0 1 1 1 a a 8 1 0 0 0 a b 9 1 0 0 1 a b if seed = 1, tr ansmit seed immediately . 10 1 0 1 0 a b 11 1 0 1 1 a b 12 1 1 0 0 a b ir mode 13 1 1 0 1 a b ir mode 14 1 1 1 0 a b ir mode 15 1 1 1 1 a b ir mode HCS360 ds40152c -page 10 preliminary ? 1996 microchip technology inc. 3.5.10 manch: manchester code modulation manch selects betw een manchester code modulation and pwm modulation. if manch = 1, manchester code modulation is selected: if manch = 0, pwm modulation is selected. 3.5.11 o vr: ov erflo w t he o v er o w bit is used to e xtend the n umber of possi- b le synchronization v alues . the synchronization counter is 16 bits in length, yielding 65,536 v alues bef ore the cycle repeats . under typical use of 10 oper ations a da y , this will pro vide near ly 18 y ears of use bef ore a repeated v alue will be used. should the system designer conclude that is not adequate , then the o v er o w bit can be utiliz ed to e xtend the n umber of unique v alues . this can be done b y prog r amming o vr t o 1 at the time of production. the encoder will automat- ically clear o vr t he rst time that the tr ansmitted s yn- chronization v alue wr aps from 0xffff to 0x0000. once cleared, o vr c annot be set again, thereb y creat- ing a per manent record of the counter o v er o w . this pre v ents f ast cycling of 64k counter . if the decoder sys- tem is prog r ammed to tr ac k the o v er o w bits , then the eff ectiv e n umber of unique synchronization v alues can be e xtended to 128k. if prog r ammed to z ero , the sys- tem will be compatib le with the ntq104/5/6 de vices (i.e ., no o v er o w with discr imination bits set to z ero). 4.0 t ransmitted w or d 4.1 t ransmission format (pwm) the HCS360 tr ansmission is made up of se v er al par ts ( figure 4-1 and figure 4-2 ). each tr ansmission is begun with a preamb le and a header , f ollo w ed b y the encr ypted and then the x ed data. the actual data is 67 bits which consists of 32 bits of encr ypted data and 3 5 b its of x ed data. each tr ansmission is f ollo w ed b y a guard per iod bef ore another tr ansmission can begin. ref er to t ab le 8-4 and t ab le 8-5 f or tr ansmission timing speci cations . the encr ypted por tion pro vides up to f our billion changing code combinations and includes the function b its (based on which b uttons w ere acti- v ated) along with the synchronization counter v alue and d iscr imination v alue . the n o n-encr ypted p or tion is compr ised of the crc bits , v low b its , the function bits and the 28/32-bit ser ial n umber . the encr ypted a nd non- encr ypted sections combined increase the n umber of combinations to 1.47 x 10 20 . 4.2 code w or d or ganization the HCS360 tr ansmits a 67-bit code w ord when a b ut- ton is pressed. the 67-bit w ord is constr ucted from a fix ed code por tion and an encr ypted code por tion ( figure 4-3 ). the encr ypted data is gener ated from 4 function b its , 2 user b its , o v er o w bit, independent mode bit, and 8 ser ial n umber bits , and the 16-bit synchronization v alue ( figure 8-4 ). the non-encr ypted code data is made up of a v low bit, 2 crc bits , 4 function bits , and the 28-bit ser ial n umber . if the e xtended ser ial n umber (32 bits) is selected, the 4 function code bits will not be tr ansmit- ted. HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 11 figure 4-1: t ransmission format?anch = 0 figure 4-2: t ransmission format?anch = 1 figure 4-3: code w or d organiza tion (right-most bit is cloc ked out fir st) logic "1" code w ord guard time preamb le sync encr ypted tx data fix ed code data bit logic "0" 1 2 3 5 7 9 4 6 8 10 t e code w ord: t o t al transmission: preamb le sync encr ypt fix ed guard 1 code w ord 1 2 4 5 6 preamb le sync encr ypt 13 14 15 16 t e t e guard time preamb le sync encr ypted d ata fix ed code data logic "0" 1 2 3 4 bpw code w ord: t o t al transmission: sync encr ypt fix ed guard 1 code w ord 1 2 4 5 6 preamb le sync encr ypt 13 14 15 16 logic "1" star t bit stop bit code w ord preamb le fix ed code data encr ypted code data 67 bits of data t r ansmitted msb ls b crc (2 bit) v low (1 bit) button status (4 bits) 28-bit ser ial number button status (4 bits) discr imination bits (12 bits) 16-bit synch v alue crc (2 bit) v low bit + ser ial number and button status (32 bits) + 32 bits of encr ypted data HCS360 ds40152c -page 12 preliminary ? 1996 microchip technology inc. 5.0 special fea tures 5.1 code w or d completion code w ord completion is an automatic f eature that ens ure s that the entire code w ord is tr ansmitted, e v en if the b utton is released bef ore the tr ansmission is com- plete and that a minim um of tw o w ords are completed. the HCS360 encoder po w ers itself up when a b utton is pushed and po w ers itself do wn after tw o complete w ords are tr ansmitted if the user has already released the b utton. if the b utton is held do wn be y ond the time f or one tr ansmission, then m ultiple tr ansmissions will result. if another b utton is activ ated dur ing a tr ansmission, the activ e tr ansmission will be abor ted and the ne w code will be gener ated using the ne w b utton inf or mation. 5.2 lo ng gu ar d ti me f eder al comm unications commission (fcc) par t 15 r ules specify the limits on fundamental po w er and har monics that can be tr ansmitted. p o w er is calculated on the w orst case a v er age po w er tr ansmitted in a 100ms windo w . it is theref ore adv antageous to minimiz e the duty cycle of the tr ansmitted w ord. this can be achie v ed b y minimizing the duty cycle of the individual bits and b y e xtending the guard time betw een tr ansmissions . long guard time (lngrd) is used f or reducing the a v er age po w er of a tr ansmission. this is a selectab le f eature . using the lngrd allo ws the user to tr ansmit a higher amplitude tr ansmission if the tr ansmission time per 100 ms is shor ter . the fcc puts constr aints on the a v er age po w er that can be tr ansmitted b y a de vice , and lngrd eff ectiv ely pre v ents contin uous tr ansmission b y only allo wing the tr ansmission of e v er y second w ord. this reduces the a v er age po w er tr ansmitted and hence , assists in fcc appro v al of a tr ansmitter de vice . 5.3 crc (cyc le redundanc y chec k) bits the crc bits are calculated on the 65 pre viously tr ans- mitted bits . the crc bits can be used b y the receiv er to chec k the data integ r ity bef ore processing star ts . the crc can detect all single bit and 66 % o f doub le bit errors . the crc is computed as f ollo ws: eq u a tion 5-1: crc calculation and with and di n the nth tr ansmission bit 0 n 64 5.4 secure learning in order to increase the le v el of secur ity in a system, it is possib le f or the receiv er to implement what is kno wn as a secure lear n ing function. this can be done b y utilizing the seed v alue on the HCS360 which is stored in eepr om . instead of the nor mal k e y gener ation method being used to create the encr yption k e y , this seed v alue is used and there should n ot be an y mathematical rela- tionship betw een ser ial n umbers and seeds f or the best secur ity . 5.5 a uto-shutoff t he a uto-shutoff function automatically stops the de vice from tr ansmitting if a b utton inadv er tently gets pressed f or a long per iod of time . this will pre v ent the de vice from dr aining the batter y if a b utton gets pressed while the tr ansmitter is in a poc k et or purse . this func- tion can be enab led or disab led and is selected b y set- ting or clear ing the time-out bit ( section 3.5.5 ). setting this bit w ill enab le the function (tur n a uto-shutoff func- tion on) and clear ing t he bit w ill disab le the function. time-out per iod is appro ximately 25 seconds . 5.6 v low : v olta g e lo w indicator the v low b it is tr ansmitted with e v er y tr ansmission ( figure 4-2 ) and will be tr ansmitted as a one if the oper ating v oltage has dropped belo w the lo w v oltage tr ip point , appro ximately 3.8v at 25 c . t his v low s ignal is tr ansmitted so the receiv er can giv e an indicat ion t o the user that the tr ansmitter batter y is lo w . 5.7 led output operation dur ing nor mal tr ansmission the led output is lo w . if the supply v oltage drops belo w the lo w v oltage tr ip point, the led output will be toggled at appro ximately 1hz dur ing the tr ansmission . c r c 1 [ ] n 1 + c r c 0 [ ] n d i n = c r c 0 [ ] n 1 + c r c 0 [ ] n d i n ( ) c r c 1 [ ] n = c r c 1 0 , [ ] 0 0 = HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 13 6.0 p r ogramming the HCS360 when using the HCS360 in a system, the user will ha v e to prog r am some par ameters into the de vice including the ser ial n umber and the secret k e y bef ore it can be used. the prog r amming a llo ws the user to input all 192 bits in a ser ial data stream, which are then stored inter nally in eepr om. prog r amming will be initiated b y f orcing the pwm line high, after the s3 line has been held high f or the appropr iate length of time . s0 and s1 should be held lo w dur ing the entire prog r am cycle ( t ab le 6-1 and figure 6-1 ). the de vice can then be pro- g r ammed b y cloc king in 16 bits at a time , f ollo w ed b y the w ord s complement u sing s3 or s2 as the cloc k line and pwm as the data in line . after each 16-bit w ord is loaded, a prog r amming dela y is required f or the inter nal prog r am cycle to complete . the ac kno wledge can read bac k after the prog r amming dela y ( t wc ). a fter the rst w ord and its complement ha v e been do wnloaded, an automatic b ulk wr ite is perf or med. t his dela y can tak e up to t wc. at the end of the prog r amming cycle , the de vice can be v er i ed ( figure 6-2 ) b y reading bac k the eepr om. reading is done b y cloc king the s3 line and reading the data bits on pwm. f or secur ity reasons , it is not possib le to e x ecute a v er ify function without rst prog r amming the eepr om. a verify operation can onl y be done once , immediatel y f ollo wing the pr o- gram c yc le . figure 6-1: pr ogramming w a vef orms figure 6-2: v erify w a vef orms t able 6-1 pr ogramming/verify timing requirements v dd = 5.0v 10% 25 c 5 c p arameter symbol min. max. units prog r am mode setup time t 2 0 4. 0 ms hold time 1 t 1 9.0 ms prog r am cycle time t wc 3 0 ms cloc k lo w time t clkl 25 m s cloc k high time t clkh 25 m s data setup time t ds 0 m s data hold time t dh 18 m s data out v alid time t dv 24 m s pwm enter prog r am mode (data) (cloc k) bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16 bit 17 t 1 t 2 repeat 12 times f or each w ord t clkh t clkl t wc t ds s2/ s3 data f or w ord 0 (key_0) data f or w ord 1 t dh bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 note 1: un used b utton inputs to be held to g round dur ing the entire prog r amming sequence . 2: the v dd pin m ust be tak en to g round after a prog r am/v er ify cycle . ac kno wledge pwm (cloc k) (data) note: if a v er ify oper ation is to be done , then it m ust immediately f ollo w the prog r am cycle . end of prog r amming cycle begin v er ify cycle here bit 1 bit 2 bit 3 bit 15 bit 14 bit 16 bit 17 bit190 bit191 t wc data in w ord 0 t dv s2/ s3 bit 0 bit191 bit190 HCS360 ds40152c -page 14 preliminary ? 1996 microchip technology inc. 7.0 integrating the HCS360 into a system use of the HCS360 in a system requires a compatib le decoder . this decoder is typically a microcontroller with compatib le r mw are . f ir mw are routines that accept tr ansmissions from the HCS360 and decr ypt the hopping code por tion of the data stream are a v ailab le . these routines pro vide system designers the means to de v elop their o wn decoding system. 7.1 learning a t ransmitter to a receiver in order f or a tr ansmitter to be used with a decoder , the tr ansmitter m ust rst be ?ear ned? se v er al lear ning str ategies can be f ollo w ed in the decoder implementa- tion. when a tr ansmitter is lear ned to a decoder , it is suggested that the decoder store s the ser ial n umber and current synchronization v alue in eepr om. the decoder m ust k eep tr ac k of these v alues f or e v er y tr ansmitter that is lear ned ( figure 7-1 ). the maxim um n umber of tr ansmitters that can be lear ned is only a function of ho w m uch eepr om memor y stor age is a v ailab le . the decoder m ust also store the man uf ac- turer s code in order to lear n a tr ansmission tr ansmitter , although this v alue will not change in a typical system so it is usually stored as par t of the microcontroller r om code . stor ing the man uf acturer s code as par t of the r om code is also better f or secur ity reasons . it m ust be stated that some lear ning str ategies ha v e been patented and care m ust be tak en not to infr inge . figure 7-1: typical learn sequence enter lear n mode w ait f or reception of a v alid code gener ate k e y from ser ial number use gener ated k e y to decr ypt compare discr imination v alue with fix ed v alue equal w ait f or reception of second v alid code compare discr imination v alue with fix ed v alue use gener ated k e y to decr ypt equal counters encr yption k e y ser ial n umber synchronization counter sequential ? ? ? exit lear n successful store: lear n unsuccessful no no no y es y es y es HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 15 7.2 decoder operation in a typical decoder oper ation ( figure 7-2 ), the k e y gen- er ation on the decoder side is done b y taking the ser ial n umber from a tr ansmission and combining that with the man uf acturer s code to create the same secret k e y that w as used b y the tr ansmitter . once the secret k e y is obtained, the rest of the tr ansmission can be decr ypted. the decoder w aits f or a tr ansmission and immediately can chec k the ser ial n umber to deter mine if it is a lear ned tr ansmitter . if it is , it tak es the encr ypted por tion of the tr ansmission and decr ypts it using the stored k e y it uses the discr imination bits to deter mine if the decr yption w as v alid. if e v er ything up to this point is v alid, the synchronization v alue is e v aluated. figure 7-2: typical decoder operation 7.3 sync hr onization with decoder the k ee l oq technology f eatures a sophisticated synchronization technique ( figure 7-3 ) which does not require the calculation and stor age of future codes . if the stored counter v alue f or that par ticular tr ansmitter and the counter v alue that w as just decr ypted are within a f or matted windo w of sa y 1 6, the counter is stored and the command is e x ecuted. if the counter v alue w as not within the single oper ation windo w , b ut is within the doub le oper ation windo w of sa y 32k windo w , the tr ans- mitted synchronization v alue is stored in tempor ar y location and it goes bac k to w aiting f or another tr ans- mission. when the ne xt v alid tr ansmission is receiv ed, it will chec k the ne w v alue with the one in tempor ar y stor age . if the tw o v alues are sequential, it is assumed that the counter had just gotten out of the single oper a- tion ?indo w? b ut is no w bac k in sync , so the ne w syn- chronization v alue is stored and the command e x ecuted. if a tr ansmitter has someho w gotten out of the doub le oper ation windo w , the tr ansmitter will not w or k and m ust be relear ned. since the entire windo w rotates after each v alid tr ansmission, codes that ha v e been used are par t of the ? loc k ed ( 32k ) codes and are no longer v alid. this eliminates the possibility of g r ab- bing a pre vious code and retr ansmitting t o gain entr y . figure 7-3: sync hr onization windo w ? t r ansmission receiv ed does ser ial number match ? decr ypt t r ansmission is decr yption v alid ? is counter within 16 ? is counter within 32k ? update counter ex ecute command sa v e counter in t emp location star t no no no no y es y es y es y es y es no and no note: the synchronization method descr ibed in this section is only a typical implementation and because it is usually implemented in r mw are , it can be altered to t the needs of a par ticular system bloc k ed entire windo w rotates to eliminate use of pre viously used codes current p osition (32k codes) doub le oper ation (32k codes) single oper ation windo w (16 codes) HCS360 ds40152c -page 16 preliminary ? 1996 microchip technology inc. 8.0 electrical chara cteristics t able 8-1 absolute maximum ra tings symbol item rating units v dd supply v oltage -0.3 to 6. 9 v v in input v oltage -0.3 to v dd + 0.3 v v out output v oltage -0.3 to v dd + 0.3 v i out max output current 25 ma t stg stor age temper ature -55 to +125 c (note) t lsol lead solder ing temp 300 c (note) v esd esd r ating 4000 v note: stresses abo v e those listed under ?bsolute maximum ra tings ma y cause per manent damage to the de vice . t able 8-2 dc chara cteristics commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c 2.0v < v dd < 3. 3 3.0 < v dd < 6. 6 p arameter sym. min t yp 1 max min t y p 1 max uni t conditions oper ating current (a vg) i cc 0.3 1. 2 0.7 1. 6 ma v dd = 3. 3v v dd = 6.6v standb y curren t i ccs 0.1 1 .0 0.1 1.0 m a a uto-shutoff current 2,3 i ccs 40 75 160 350 m a high le v el input v oltage v ih 0. 55 v d d v dd + 0. 3 0. 55v d d v dd + 0. 3 v lo w le v el input v oltage v il -0.3 0. 15 v d d -0.3 0. 15 v d d v high le v el output v oltage v oh 0. 7v dd 0. 7v dd v i oh = -1.0ma, v dd = 2.0v i oh = - 2.0ma , v dd = 6.6v lo w le v el output v oltage v ol 0.08 v d d 0.08 v d d v i ol = 1.0ma, v dd = 2.0v i ol = 2 .0ma , v dd = 6.6v led sink current i led 0.15 1.0 4.0 0.15 1.0 4.0 ma v led = 1.5v, v dd = 6.6v resistance; s0-s3 r s 0- 3 40 60 80 40 60 80 k w v dd =4.0v resistance; pwm r pw m 80 120 1 60 80 120 160 k w v dd =4.0v note 1: t ypical v alues are at 25 c . 2: a uto-shutoff current speci cation does not include the current through the input pulldo wn resistors . 3: a uto-shutoff current is per iodically sampled and not 100% tested. HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 17 figure 8-1: p o wer up and transmit timing figure 8-2: pwm f ormat (manch = 0) figure 8-3: pwm preamb le/header f ormat t able 8-3 po wer up and transmit timing requirements v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c p arameter symbol min max unit remarks time to second b utton press t bp 10 + code w ord time 26 + code w ord time ms ( note 1 ) t r ansmit dela y from b utton detect t td 4.5 26 ms ( note 2 ) debounce dela y t db 4.0 13 ms a uto-shutoff time-out per iod t to 15.0 35 s ( note 3 ) note 1: t bp is the time in which a second b utton can be pressed without completion of the rst code w ord and the intention w as to press the combination of b uttons . 2: t r ansmit dela y maxim um v alue if the pre vious tr ansmission w as successfully tr ansmitted. 3: the auto shutoff timeout per iod is not tested. button press sn detect t db pwm t td code w ord t r ansmission t to code w ord 1 code w ord 2 code w ord 3 code w ord n t bp logic ? logic ? preamb le header encr ypted p or tion of t r ansmission fix ed por tion o f t r ansmission guard time t p t h t hop t fix t g t bp t e t e t e preamb le header 3 2 t e 10 t e data w ord t r ansmission bit 0 bit 1 HCS360 ds40152c -page 18 preliminary ? 1996 microchip technology inc. figure 8-4: pwm data w or d f ormat figure 8-5: manc hester f ormat (manch = 1) figure 8-6: manc hester preamb le/header f ormat bit 0 bit 1 header bit 30 bit 31 bit 32 bit 33 bit 58 bit 59 fix ed code data encr ypted data guard lsb lsb msb msb s3 s0 s1 s2 v low crc0 crc1 time ser ial number function code status bit 60 bit 61 bit 62 bit 63 bit 64 bit 65 crc bit 66 logic ? logic ? preamb le header encr ypted p or tion of t r ansmission fix ed por tion o f t r ansmission guard time t p t h t hop t fix t g t bp t e t e preamb le header 3 2 t e 4 t e data w ord t r ansmission bit 0 bit 1 figure 8-7: HCS360 normaliz ed t e vs. t emp 0.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.7 0.6 t e min. t e max. v dd legend = 2.0 v = 3.0 v = 6.0 v t ypical t e t emper ature c -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 19 t able 8-4 code w or d t ransmission timing p arameter s?wm mode v dd = +2.0v to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast1 = 0, f ast0 = 0 f ast1 = 0, f ast0 = 1 symbol characteristic number of t e min. t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 260 400 620 1 130 200 310 m s t bp pwm bit pulse width 3 780 1200 1860 3 390 600 930 m s t p preamb le dur ation 32 8.3 12.8 19.8 32 4.2 6.4 9.9 ms t h header dur ation 10 2.6 4.0 6.2 10 1.3 2.0 3.1 ms t hop hopping code dur ation 96 25.0 38.4 59.5 96 12.5 19.2 29.8 ms t fix fix ed code dur ation 105 27.3 42.0 65.1 105 13.7 21.0 32.6 ms t g guard time (lngrd = 0) 16 4.2 6.4 9.9 32 4.2 6.4 9.9 ms t otal tr ansmit time 259 67.3 103.6 160.6 275 35.8 55.0 85.3 ms pwm data r ate 1282 833 538 2564 1667 1075 bps note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. v dd = +2.0v to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast1 = 1, f ast0 = 0 f ast1 = 1, f ast0 = 1 symbol characteristic number of t e min. t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 130 200 310 1 65 100 155 m s t bp pwm bit pulse width 3 390 600 930 3 195 300 465 m s t p preamb le dur ation 32 4.2 6.4 9.9 32 2.1 3.2 5.0 ms t h header dur ation 10 1.3 2.0 3.1 10 0.7 1.0 1.6 ms t hop hopping code dur ation 96 12.5 19.2 29.8 96 6.2 9.6 14.9 ms t fix fix ed code dur ation 105 13.7 21.0 32.6 105 6.8 10.5 16.3 ms t g guard time (lngrd = 0) 32 4.2 6.4 9.9 64 4.2 6.4 9.9 ms t otal tr ansmit time 275 35.8 55.0 85.3 307 20.0 30.7 47.6 ms pwm data r ate 2564 1667 1075 5128 3333 2151 bps note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. HCS360 ds40152c-page 20 preliminary ? 1996 microchip technology inc. table 8-5 code word transmission timing parameters?anchester mode v dd = +2.0v to 6.6v commercial (c):tamb = 0 c to +70 c industrial (i):tamb = -40 c to +85 c code words transmitted fast1 = 0, fast0 = 0 fast1 = 0, fast0 = 1 symbol characteristic number of t e min. typ. max. number of te min. typ. max. units t e basic pulse element 1 520 800 1240 1 260 400 620 m s t p preamble duration 32 16.6 25.6 39.7 32 8.3 12.8 19.8 ms t h header duration 4 2.1 3.2 5.0 4 1.0 1.6 2.5 ms t start start bit 2 1.0 1.6 2.5 2 0.5 0.8 1.2 ms t hop hopping code duration 64 33.3 51.2 79.4 64 16.6 25.6 39.7 ms t fix fixed code duration 70 36.4 56.0 86.8 70 18.2 28.0 43.4 ms t stop stop bit 2 1.0 1.6 2.5 2 0.5 0.8 1.2 ms t g guard time (lngrd = 0) 8 4.2 6.4 9.9 16 4.2 6.4 9.9 ms total transmit time 182 94.6 145.6 223.7 196 50.76 78.4 121.5 ms manchester data rate 1923 1250 806 3846.2 2500 1612.9 bps note: the timing parameters are not tested but derived from the oscillator clock. v dd = +2.0v to 6.6v commercial (c):tamb = 0 c to +70 c industrial (i):tamb = -40 c to +85 c code words transmitted fast1 = 1, fast0 = 0 fast1 = 1. fast0 = 1 symbol characteristic number of t e min. typ. max. number of te min. typ. max. units t e basic pulse element 1 260 400 620 1 130 200 310 m s t p preamble duration 32 8.3 12.8 19.8 32 4.2 6.4 9.9 ms t h header duration 4 1.0 1.6 2.5 4 0.5 0.8 1.2 ms t start start bit 2 0.5 0.8 1.2 2 0.3 0.4 0.6 ms t hop hopping code duration 64 16.6 25.6 39.7 64 8.3 12.8 19.8 ms t fix fixed code duration 70 18.2 28.0 43.4 70 9.1 14.0 21.7 ms t stop stop bit 2 0.5 0.8 1.2 2 0.3 0.4 0.6 ms t g guard time (lngrd = 0) 16 4.2 6.4 9.9 32 4.2 6.4 9.9 ms total transmit time 196 50.96 78.4 121.5 212 27.6 42.4 65.7 ms manchester data rate 3846.2 2500.0 1612.9 7692.3 5000.0 3225.8 bps note: the timing parameters are not tested but derived from the oscillator clock. HCS360 ? 1996 microchip technology inc. preliminary ds40152c -page 21 notes: HCS360 ds40152c -page 22 preliminary ? 1996 microchip technology inc. notes: HCS360 ? 1996 microchip technology inc. preliminary ds40152c-page 23 HCS360 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. sales and suppor t package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0?c to +70?c range: i = ?0?c to +85?c device: HCS360 code hopping encoder HCS360t code hopping encoder (tape and reel) HCS360 /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e (see last page) 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip s bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. inf or mation contained in this pub lication regarding de vice applications and the lik e is intended f or suggestion only and ma y be superseded b y updates . no representation or w arr anty is giv en and no liability is assumed b y microchip t echnology incor por ated with respect to the accur acy or use of such inf or mation, or infr ingement of patents or other intellectual proper ty r ights ar ising from such use or otherwise . use of microchip s products as cr itical components in lif e suppor t systems is not author iz ed e xcept with e xpress wr itten appro v al b y microchip . no licenses are con v e y ed, implicitly or otherwise , under an y intellectual proper ty r ights . the microchip logo and name are registered tr ademar ks of microchip t echnology inc. in the u .s .a. and other countr ies . all r ights reser v ed. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . ds40152c -page 24 preliminary ? 1997 microchip technology inc. w orldwide s ales & s ervice americas corporate of ce microchip t echnology inc. 2355 w est chandler blvd. chandler , az 85224-6199 t el: 602-786-7200 f ax: 602-786-7277 t echnical suppor t: 602 786-7627 w eb: http://www .microchip .com atlanta microchip t echnology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el: 770-640-0034 f ax: 770-640-0307 boston microchip t echnology inc. 5 mount ro y al a v en ue mar lborough, ma 01752 t el: 508-480-9990 f ax: 508-480-8575 chica go microchip t echnology inc. 333 pierce road, suite 180 itasca, il 60143 t el: 708-285-0071 f ax: 708-285-0075 dallas microchip t echnology inc. 14651 dallas p ar kw a y , suite 816 dallas , tx 75240-8809 t el: 972-991-7177 f ax: 972-991-8588 da yton microchip t echnology inc. t w o prestige place , suite 150 miamisb urg, oh 45342 t el: 937-291-1654 f ax: 937-291-9175 los ang eles microchip t echnology inc. 18201 v on kar man, suite 1090 ir vine , ca 92612 t el: 714-263-1888 f ax: 714-263-1338 ne w y ork microchip t echnology inc. 150 motor p ar kw a y , suite 416 hauppauge , ny 11788 t el: 516-273-5305 f ax: 516-273-5335 san jose microchip t echnology inc. 2107 nor th first street, suite 590 san jose , ca 95131 t el: 408-436-7950 f ax: 408-436-7955 t or onto microchip t echnology inc. 5925 air por t road, suite 200 mississauga, ontar io l4v 1w1, canada t el: 905-405-6279 f ax: 905-405-6253 asia/p a cific hong k ong microchip asia p aci c rm 3801b , t o w er t w o metroplaza 223 hing f ong road kw ai f ong, n.t ., hong k ong t el: 852-2-401-1200 f ax: 852-2-401-3431 india microchip t echnology india no . 6, legacy , con v ent road bangalore 560 025, india t el: 91-80-299-4036 f ax: 91-80-559-9840 k orea microchip t echnology k orea 168-1, y oungbo bldg. 3 floor samsung-dong, kangnam-k u seoul, k orea t el: 82-2-554-7200 f ax: 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden br idge bldg. 2077 y an?n road w est, hongiao distr ict shanghai, prc 200335 t el: 86-21-6275-5700 f ax: 86 21-6275-5060 singapore microchip t echnology t aiw an singapore br anch 200 middle road #10-03 pr ime centre singapore 188980 t el: 65-334-8870 f ax: 65-334-8850 t aiwan, r.o .c microchip t echnology t aiw an 10f-1c 207 t ung hua nor th road t aipei, t aiw an, r oc t el: 886 2-717-7175 f ax: 886-2-545-0139 eur ope united kingdom ar iz ona microchip t echnology ltd. unit 6, the cour ty ard meado w bank, fur long road bour ne end, buc kinghamshire sl8 5aj t el: 44-1628-851077 f ax: 44-1628-850259 france ar iz ona microchip t echnology sarl zone industr ielle de la bonde 2 rue du buisson aux f r aises 91300 massy , f r ance t el: 33-1-69-53-63-20 f ax: 33-1-69-30-90-79 german y ar iz ona microchip t echnology gmbh gusta v-heinemann-ring 125 d-81739 m?chen, ger man y t el: 49-89-627-144 0 f ax: 49-89-627-144-44 ital y ar iz ona microchip t echnology srl centro direzionale colleone p alazz o t aur us 1 v . le colleoni 1 20041 ag r ate br ianza milan, italy t el: 39-39-6899939 f ax: 39-39-6899883 j ap an microchip t echnology intl. inc. bene x s-1 6f 3-18-20, shin y ok ohama k ohoku-k u, y ok ohama kanaga w a 222 j apan t el: 81-4-5471- 6166 f ax: 81-4-5471-6122 1/14/97 pr inted on recycled paper . all r ights reser v ed. ?1997, microchip t echnology incor por ated, usa. 1/97 m |
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